- CXMT has begun mass production of DRAM on its fifth-generation process, which it says rivals the most advanced chips from Samsung and SK hynix.
- The figures are CXMT’s own and hard to compare with rivals’, and the company has not disclosed yields or output.
China’s largest DRAM maker, ChangXin Memory Technologies (CXMT), has begun mass production on its fifth-generation manufacturing process, known as G5. The company says the process now comes close to the most advanced memory production at Samsung and SK hynix, even though CXMT has no access to the EUV lithography machines its Korean rivals use.
The headline figure is 11.95nm, the half-pitch of CXMT’s memory array. Half-pitch is half the distance between the repeating lines of memory cells on a chip, so a smaller number means more cells fit in the same space. CXMT says that density gain yields at least 50% more chips from each silicon wafer than its previous generation.
CXMT announced the milestone on Sunday at the 2026 World Manufacturing Convention in Hefei, alongside two LPDDR5X mobile memory chips built on G5. Both carry 24Gb per die, a 50% increase over CXMT’s previous generation. They come in 496-ball and 245-ball packages for smartphones and portable electronics, and CXMT said both are already in mass production.
According to Reuters, Luo Xiaodong, CXMT’s vice president and head of its marketing centre, said the company’s process capability is now on par with the most advanced processes in volume production.
How CXMT scaled DRAM without EUV
CXMT credits the 11.95nm figure to self-aligned quadruple patterning (SAQP). The technique uses repeated deposition and etch steps to multiply the line density printed by a single lithography exposure. That lets deep ultraviolet (DUV) scanners produce features finer than they could in one pass.
The choice is largely forced on CXMT. ASML has not been permitted to ship EUV systems to Chinese customers, while Samsung and SK hynix use EUV on their leading DRAM nodes. CXMT’s release does not mention EUV.
The company listed other process gains. The array capacitor aspect ratio reaches 45:1, which CXMT attributes to a reworked process flow and new materials. A high-k metal gate (HKMG) process adapted for DRAM cut the core area height to 6,762nm. CXMT also said it built a digital twin platform, covering everything from design to yield maintenance, to shorten development cycles.
The release does not say what that 50% density gain costs to achieve. Semiconductor Engineering has noted that SAQP adds manufacturing complexity, because small variations in deposition, etching or the dimensions of the initial pattern can build up across the multiple steps. The result is uneven line spacing, known in the industry as pitch walk. CXMT says G5 improves power efficiency and cost competitiveness, but it has not disclosed yields that would show how well it is controlling those variations.
Reading the fine print on CXMT’s G5 claims
A note at the bottom of CXMT’s release qualifies the headline figures. The half-pitch, aspect ratio and core height are the company’s own physical measurements, subject to standard metrology margins of error. The percentage gains are measured against CXMT’s previous platform. Die-per-wafer figures are normalised to a baseline, which the Seoul Economic Daily reported as an 8Gb-equivalent basis.
The comparison with Samsung and SK hynix is also less direct than the announcement suggests. The South China Morning Post reported that the Korean leaders produce on 10nm-class process technology. The Seoul Economic Daily noted that 11.95nm measures one specific structure and is difficult to compare with the 12nm-class node names used by Samsung, SK hynix and Micron. Semiconductor Engineering puts active-area pitch at 1b-class DRAM, a generation Samsung and SK hynix already have in volume production, at roughly 22 to 26nm. CXMT’s 11.95nm half-pitch equals a pitch of about 23.9nm, within that range.DRAM makers have long used generation labels rather than literal dimensions, and each defines its generations differently.
CXMT also did not disclose G5 yields or monthly output. Until an independent teardown examines G5 chips, the 11.95nm figure rests on CXMT’s data alone.
Why the timing matters for DRAM supply
The announcement comes as CXMT’s commercial position strengthens. TrendForce data shows the company’s share of global DRAM revenue rose from 7.6% to 9.5% in the second quarter of 2026, with sales nearly doubling from the previous quarter. That ranks it fourth, behind Samsung at 39.4%, SK hynix at 24.9% and Micron at 23.3%.
Reuters also reported that CXMT raised RMB57.92 billion (US$8.6 billion) in its STAR Market IPO in July, Asia’s largest this year, and is planning a second memory plant in Beijing. Citing sources, the report said CXMT plans a NAND flash R&D line in the capital. That move would put it in competition with Samsung and domestic rival YMTC. Earlier this month, CXMT said it had started mass production of LPDDR6, rated at up to 12,800Mbps, with the chip debuting in Xiaomi’s 18 Fold.
Industry observers cited by Chosun Ilbo said chips from CXMT and YMTC still trail Samsung and SK hynix on performance. However, they said the Chinese makers could take global share by competing on price while memory supply stays tight. Reuters reported that the same supply constraints have given CXMT and YMTC more leverage with domestic customers.
Some of that effect is already visible. According to the Seoul Economic Daily, a Taiwanese PC maker said Chinese output has grown enough that commodity memory is no longer in short supply. The same report noted that CXMT has expanded in commodity DRAM, a segment its larger rivals have de-emphasised as they prioritise AI memory. A lower-cost supplier reaching comparable density in mobile DRAM could squeeze Samsung’s and SK Hynix’s margins in exactly those segments.
CXMT’s HBM3E is reported to be in trial production. Its disclosures as a listed company may give the first clear view of whether its EUV-free route to scaling holds up in volume.
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